Student Projects

In our group research projects are conducted on various topics on Embedded Systems and Signal Processing. They are typically scheduled for a semester and may serve as a preparatory work for a master thesis.

Embedded Systems and Signal Processing

Implementation of a Phase Locked Loop (PLL) available
Implementation of synchronization methods available
Comparison of the performance of different DAC/ADCs available
Portation of an AVR softcore to the Altera DE2 FPGA demonstration board available
Implementation of interface drivers for the FPGA demonstration board available

Implementation of a Phase Locked Loop (PLL)

Status	available
Advisor	Univ.-Prof. Dr. Mario Huemer
Contact	Dipl.-Ing. Christian Lederer
E-Mail
Phone	+43 (0)463 2700 3667
Description	The aim of a phase locked loop is to track the carrier phase of an input signal. This can e.g. be done using a loop filter and a numerical controlled oscillator. In this project such a phase locked loop shall be implemented in VHDL.

Implementation of synchronization methods

Status	available
Advisor	Univ.-Prof. Dr. Mario Huemer
Contact	Dipl.-Ing. Christian Lederer
E-Mail
Phone	+43 (0)463 2700 3667
Description	In this project several methods to synchronize a receiver on a carrier wave shall be implemented. The implementation shall be done in VHDL which shall be verified with simulations and furthermore synthesized to a FPGA.

Comparison of the performance of different DAC/ADCs

Status	available
Advisor	Univ.-Prof. Dr. Mario Huemer
Contact	Dipl.-Ing. Christian Lederer
E-Mail
Phone	+43 (0)463 2700 3667
Description	Here the performance of digital-to-analog and analog-to-digital converters concepts shall be compared. The comparison can be done with an already existing hardware provided by the company Texas Instruments. Using this hardware, the converters which are build in an microcontroller shall be compared with converters in external chips. The converters can be controlled with the firmware of the microcontroller, which is written in C.

Portation of an AVR softcore to the Altera DE2 FPGA demonstration board

Status	available
Advisor	Univ.-Prof. Dr. Mario Huemer
Contact	Dipl.-Ing. Christian Lederer
E-Mail
Phone	+43 (0)463 2700 3667
Description	In this project an already existing VHDL/Verilog model for an AVR microprocessor shall be ported to the Altera DE2 demonstration baord. The goal of this project is to have a microcontroller build-in the FPGA which can be programmed by the development environment for AVR microcontrollers. Furthermore it shall be shown that e.g. the LCD display can be controlled with the firmware (written in C/C++) running on this controller.

Implementation of interface drivers for the FPGA demonstration board

Status	available
Advisor	Univ.-Prof. Dr. Mario Huemer
Contact	Dipl.-Ing. Christian Lederer
E-Mail
Phone	+43 (0)463 2700 3667
Description	The Altera DE2 demonstration board provides a lot of interfaces to communicate with the FPGA. The aim of this project is to implement some device drivers for these interfaces in VHDL. The output shall be some small VHDL cores, which can be used in a VHDL project to transmit/receive data via e.g the Ethernet, UART, USB interface to/from the FPGA.